In recent years, there has been used a technique controlling a frequency of a clock signal dynamically in order to reduce power consumption of an LSI. The technique used often is to change a dividing ratio of a clock frequency, which is called a clock-gear in general, and the technique switching the clock frequency to an equal multiple, ½ times, ¼ times, or the like has been used.
Then, in order to reduce the power consumption further, when performing low-speed operation, output of a PLL circuit is switched from a high-speed clock to a low-speed clock that bypasses the PLL (its frequency and its phase are different), and a minimum frequency in accordance with a CPU processing load is controlled dynamically, and therefore output clocks of the plural PLL circuits are selected dynamically.
However, there is a case where a clock signal having a short pulse width called a glitch is output to output of a selector when asynchronous clock signals whose operating frequency is different from each other are selected dynamically in a normal selector, and there is a possibility of causing an erroneous operation. The glitch is also called a hazard.
FIG. 15 is a circuit diagram depicting a configuration example of a clock signal selection circuit. FIG. 16 is a timing chart depicting an operation thereof. A selector 1501 selects either a first clock signal CLK_A or a second clock signal CLK_B in accordance with a clock selection signal SEL to output a clock signal SEL_CLK. As for the clock signal SEL_CLK, the first clock signal CLK_A is selected when the clock selection signal SEL is a high level, and the second clock signal CLK_B is selected when the clock selection signal SEL is a low level. However, at the time of switching of the clock selection signal SEL, there is a case where a clock having a short pulse width called a glitch 1601 occurs in the clock signal SEL_CLK, and there is a possibility that a CPU using the clock signal SEL_CLK or the like causes an erroneous operation.
FIG. 17 is a circuit diagram depicting a configuration example of another clock signal selection circuit. A phase locked-loop (PLL) circuit 1701 inputs a clock signal CLK and outputs a clock signal whose frequency is higher than that of the clock signal CLK. A selector 1702 selects either the clock signal that the PLL circuit 1701 outputs or the clock signal CLK in accordance with the clock selection signal SEL to output the clock signal SEL_CLK.
FIG. 18 is a circuit diagram depicting a configuration example of another clock signal selection circuit. A first PLL circuit 1801 inputs the first clock signal CLK_A and outputs a clock signal whose frequency is higher than that of the first clock signal CLK_A. A second PLL circuit 1802 inputs the second clock signal CLK_B and outputs a clock signal whose frequency is higher than that of the second clock signal CLK_B. A selector 1803 selects the clock signal that either the PLL circuit 1801 or the PLL circuit 1802 outputs in accordance with the clock selection signal SEL to output the clock signal SEL_CLK.
FIG. 19 is a circuit diagram depicting a configuration example of another clock signal selection circuit. A first PLL circuit 1901 inputs the first clock signal CLK_A and outputs a clock signal whose frequency is higher than that of the first clock signal CLK_A. A second PLL circuit 1902 inputs the second clock signal CLK_B and outputs a clock signal whose frequency is higher than that of the second clock signal CLK_B. A selector 1903 selects either the clock signal that the PLL circuit 1901 outputs or the first clock signal CLK_A in accordance with a clock selection signal SEL0 to output a clock signal. A selector 1904 selects the clock signal that either the selector 1903 or the PLL circuit 1902 outputs in accordance with a clock selection signal SELL to output a clock signal CPU1_CLK to a first CPU (a central processing unit) 1907. A selector 1905 selects the clock signal that either the selector 1903 or the PLL circuit 1902 outputs in accordance with a clock selection signal SEL2 to output a clock signal CPU2_CLK to a second CPU 1908. A selector 1906 selects the clock signal that either the selector 1903 or the PLL circuit 1902 outputs in accordance with a clock selection signal SEL3 to output a clock signal CPU3_CLK to a third CPU 1909. The CPUs 1907 to 1909 can write the clock selection signals SEL0 to SEL3 in a clock control register 1911 through a bus 1910. The register 1911 outputs the clock selection signals SEL0 to SEL3 to the selectors 1903 to 1906. The CPUs 1907 to 1909 can set the clock signals CPU1_CLK to CPU3_CLK different from one another, and therefore it is difficult to comprehend a frequency of its own current clock signal.
FIG. 20 is a circuit diagram depicting a configuration example of another clock signal selection circuit. FIG. 21 and FIG. 22 are timing charts depicting an operation thereof. There are depicted, in the order from the top, the first clock signal CLK_A, the second clock signal CLK_B, the clock selection signal SEL, an output signal FF_A1/Q from a flip-flop FF_A1, an output signal FF_A2/Q from a flip-flop FF_A2, an output signal from a gated clock buffer GCLK_A, an output signal FF_B1/Q from a flip-flop FF_B1, an output signal FF_B2/Q from a flip-flop FF_B2, an output signal from a gated clock buffer GCLK_B and the clock signal SEL_CLK in FIG. 21.
The flip-flop FF_A1 inputs the clock selection signal SEL to output a signal in synchronization with the first clock signal CLK_A. The flip-flop FF_A2 inputs the output signal from the flip-flop FF_A1 to output a signal in synchronization with the first clock signal CLK_A. The flip-flops FF_A1 and FF_A2 are preset to hold a high level at the time of initialization. The clock selection signal SEL is an asynchronous signal with respect to the first clock signal CLK_A, and therefore the flip-flop FF_A1 has a possibility of outputting an indefinite value. Even when the flip-flop FF_A1 outputs the indefinite value, the flip-flop FF_A2 can determine an output value and prevent the indefinite value from propagating to a subsequent stage.
The gated clock buffer GCLK_A is a latch-type gated clock buffer, and has a latch circuit 101a and an AND circuit 102a. As depicted in FIG. 22, the latch circuit 101a inputs the output signal from the flip-flop FF_A2 as a signal LT1, and outputs the input signal LT1 as an output signal LT2 as it is when the first clock signal CLK_A is a low level. When the first clock signal CLK_A is a high level, the latch circuit 101a holds the output signal LT2 in a previous state to output it. The AND circuit 102a outputs a logical product signal of the output signal LT2 from the latch circuit 101a and the first clock signal CLK_A.
Here, in the case when the latch circuit 101a in the gated clock buffer GCLK_A does not exist, the AND circuit 102a outputs a logical product signal AND1 of the signal LT1 and the clock signal CLK_A depicted in FIG. 22. This logical product signal AND1 has a faster timing of a pulse than that of the signal GCLK_A, and therefore a condition of set up time becomes severe. Providing the latch circuit 101a delays the timing of the pulse of the signal GCLK_A, and therefore the condition of set up time can be loosened.
An inverter INV_B1 outputs a logical inversion signal of the clock selection signal SEL. The flip-flop FF_B1 inputs the output signal from the inverter INV_B1 to output a signal in synchronization with the second clock signal CLK_B. The flip-flop FF_B2 inputs the output signal from the flip-flop FF_B1 to output a signal in synchronization with the second clock signal CLK_B. The flip-flops FF_B1 and FF_B2 are reset to hold a low level at the time of initialization. The clock selection signal SEL is an asynchronous signal with respect to the second clock signal CLK_B, and therefore the flip-flop FF_B1 has a possibility of outputting an indefinite value. Even when the flip-flop FF_B1 outputs the indefinite value, the flip-flop FF_B2 can determine an output value and prevent the indefinite value from propagating to a subsequent stage.
The gated clock buffer GCLK_B is a latch-type gated clock buffer, and has a latch circuit 101b and an AND circuit 102b. Similar to the gated clock buffer GCLK_A, the latch circuit 101b inputs the output signal from the flip-flop FF_B2, and outputs the input signal as an output signal as it is when the second clock signal CLK_B is a low level. When the second clock signal CLK_B is a high level, the latch circuit 101b holds the output signal in a previous state to output it. The AND circuit 102b outputs a logical product signal of the output signal from the latch circuit 101b and the second clock signal CLK_B.
An OR circuit OR_AB outputs a logical sum signal of the output signals from the AND circuits 102a and 102b as the clock signal SEL_CLK. When the clock selection signal SEL is made to be a high level, the first clock signal CLK_A can be selected to output the clock signal SEL_CLK. On the contrary, when the clock selection signal SEL is made to be a low level, the second clock signal CLK_B can be selected to output the clock signal SEL_CLK. However, immediately after the clock selection signal SEL becomes a low level, the clock signal SEL_CLK becomes a signal in which the first clock signal CLK_A and the second clock signal CLK_B are mixed, and thereby glitches 2101 and 2102 occur resulting in an erroneous operation.
FIG. 23 is another timing chart depicting the operation of the clock signal selection circuit in FIG. 20. The case when the second clock signal CLK_B is stopped will be explained. In this case, when the clock selection signal SEL is switched to a low level, a clock stopped period 2301 occurs in the clock signal SEL_CLK, which is not preferred.
Further, as a clock switching circuit, there have been suggested arts described below.
In Japanese Laid-open Patent Publication No. 2005-191877, when output is switched from a first input clock signal to a second input clock signal, based on an output signal from a first flip-flop group in which an inverted signal of a selection signal is fetched in response to the first input clock signal, an output prohibition period of the first input clock signal is started.
In Japanese Laid-open Patent Publication No. 2000-138568, although a clock signal to be output is selected by a selection signal, a switching timing is controlled by a handshake signal in synchronization with each clock signal thereby preventing interruption in the course of a pulse.